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User Testbench
Files Used in the User Testbenches
Table 8-3 lists all the VHDL and Verilog source files used in the user testbenches and gives a description of their
functions. All source files are provided with the RTL release. With the Evaluation release, only some of the source files
are provided. All others are pre-compiled into the CorePCIF simulation library.
Table 8-3 · User Testbench Source Files
File
tb_user.vhd
tb_user.v
pcisystem.vhd
pcisystem.v
memory.vhd
memory.v
fifo.vhd
fifo.v
ram2k8.vhd
ram2k8.v
fifo512x32.vhd
fifo512x32.v
coreparameters.vhd
coreparameters.v
pcimaster.vhd
pcimaster.v
pcitarget.vhd
pcitarget.v
pcimonitor.vhd
pcimonitor.v
textio.vhd
misc.vhd
Supplied
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RTL and
Obfuscated
only
RTL and
Obfuscated
only
RTL and
Obfuscated
only
RTL only
RTL only
Function
Top level of testbench. Creates a PCI bus and instantiates all the devices connected to the bus. It
also contains the procedural testbench.
Top level of the test design that includes the cores and memory blocks. This is a synthesizable
design in some families.
Top-level memory module creating the 8 k words of memory (or 16 k for 64-bit cores) used for
BAR 0
Top-level FIFO module creating the FIFOs used for BAR 1
Low-level memory block implementing the memory using FPGA memory blocks
Low-level FIFO block implementing the FIFO using FPGA FIFO blocks
Package or include file used to configure the core instantiated in the PCISYSTEM module. The
testbench file uses this to decide which tests to run. This file is auto-generated by CoreConsole
during the core generation, and the settings will match those set in the CoreConsole GUI.
PCI Master function used by the testbench to carry out PCI cycles
Simple PCI Target function that implements a PCI Target capable of responding to memory
read and write cycles
PCI bus monitor that monitors PCI activity, looking for illegal activity. Also capable of tracing
and displaying PCI activity.
VHDL package that provides the printf function used in the testbench. Not required for the
Verilog version.
VHDL package that provides some very low-level type definitions and functions. Not required
for the Verilog version.
v4.0
123
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相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
CP2-GSA-L CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1 CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4 CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F COMPACT PCI - MISC
CP2105EK KIT EVAL FOR CP2105
相关代理商/技术参数
COREPCIF-RMFL 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPRO LEDBULB 10.5-60W B 制造商:Philips Lumileds 功能描述:
COREPRO LEDBULB 10.5-60W E 制造商:Philips Lumileds 功能描述: